Semiconductor structures and devices can contain metalized layers for forming interconnects between different regions of the structure. A pattern of trenches and vias can be patterned into a dielectric layer and inlaid with metal wire to fabricate a metalized layer. A silicide can be present and the bottom of vias formed in the metalized layer to facilitate the electrical contact between the metal wire and an underlying device layer of the semiconductor structure.
Semiconductor structures containing transistor devices have a gate electrode structure for applying an electrical potential to the transistor gate. Gate-last fabrication schemes can be employed where a dummy gate is provided and other elements required to form a transistor device are fabricated around the dummy gate. The dummy gate is removed and a functional gate structure is formed at a downstream point during fabrication. Formation of a functional gate structure typically requires high-temperature thermal processes such as densify annealing, post-nitridation annealing, and drive-in annealing. However, high-temperature processes can induce damage to some materials that can be present in the semiconductor structure including silicides.